1. Field of the Invention
The present invention relates to linear regulators and, more particularly, to a low dropout regulator capable of sinking and sourcing current, and of regulating a first output voltage that is exactly half of a second output voltage.
2. Description of Related Art
Currently, double data rate (DDR) DRAM devices are getting popular and have the potential to replace the synchronous dynamic RAM (SDRAM) devices. As the data rate increases, the data communication between a CPU and a DDR DRAM requires careful design to minimize signal reflection and ringing. FIG. 1A shows a representative data line of a conventional data bus system. The data line is connected to ground through a termination resistor 15 (RT). A line driver 12 operates with a supply voltage of VDDQ 11, typically 2.5V. The series resistance 13 (RS) of data line 14 is typically in the order of 10 Ω. A termination resistor 15 (RT), with a typical resistance of 56 Ω, is connected to the receiving end of the data line 14 to reduce high-speed signal reflection and ringing. A plurality of line receivers, exemplified by buffers 16 and 17, are connected to the receiving end of data bus line 14. The negative inputs of buffers 16 and 17 are connected to a reference 18, which is exactly one half of VDDQ voltage, or 1.25V.
When the line driver 12 output is a high state, 2.5V, the power dissipation of the data line is VDDQ2/(RS+RT), or 94.7 mW. When the line driver 12 output is a low state, the power dissipation is 0. Assuming the line driver 12 has 50% probability in high state, and 50% probability in low state, its average power dissipation would be 47.3 mW.
FIG. 1B shows a data bus line 24 with a similar structure, but its termination resistor 25 is connected to a regulated voltage 29 (VTT), which is half of VDDQ voltage. Line driver 22 is powered by a VDDQ voltage 21, or 2.5V. The series resistance 23 of data line 24 is 10 Ω. The termination resistance 25 is 56 Ω. Buffers 26 and 27 are connected to the receiving end of data bus line 24.
When the output of line driver 22 is a high state, or 2.5V, its power dissipation is (VDDQ−VTT)2/(RS+RT), or 23.7 mW. When it is a low state, or 0V, the power dissipation is VTT2/(RS+RT), or 23.7 mW. Therefore, either in high or low state, the average power dissipation of the data line is always 23.7 mW.
The calculation above clearly shows that, by connecting the termination resistors to a voltage half of VDDQ, the power dissipation can be cut down by 50%. In a typical DDR DRAM data bus system, there may be as many as 110 data lines. The power dissipation saving will be 2.607 W, a significant amount.
However, in order to achieve power saving, the termination voltage VTT 29 requires both sinking and sourcing current capability. When there are more lines in high states than in low states, VTT 29 needs to draw (sink) current from the data bus system. On the other hand, when there are more lines in low state than in high state, VTT 29 needs to supply (source) current to the data bus system.
VDDQ 21 is typically adjustable between 2.5V and 2.8V with a maximum peak current of 5 A. VTT 29 has a maximum source or sink current of 3 A. In general, VTT 29 is required to be kept at one half of VDDQ 21 voltage.
In a typical computer system, there are 3.3V and 5V power supplies available. A switching regulator or a linear regulator is used to derive the VDDQ voltage from the 5.0V or the 3.3V power source. A linear regulator is not as efficient as a switching regulator, but it requires no inductors and very few external components, and has relatively low cost. Recently, more and more DDR DRAM systems choose linear regulators to supply the VDDQ and VTT power.